The ever-increasing data rates of wireline and wireless communication systems poses stringent performance requirements on their mixed-signal IC sub-systems. In particular, there is a great demand for high-resolution data converters at higher sampling rates, and high-performance frequency synthesizers with stringent phase-noise and spurious performance requirements. Delta-Sigma (ΔΣ) Digital-to-Analog Converters (DACs) leverage noise shaping and high oversampling ratio to realize a high-resolution (on the order of 20-bits), which cannot be readily achieved using a conventional DAC.
Similarly, ΔΣ Fractional-N Phase Locked Loops (FN-PLLs) leverage noise shaping and high oversampling ratio to realize a very fine frequency synthesis capability (on the order of 20-bits). In both of these examples, the ΔΣ noise-shaping modulator reduces the word length (m) of its digital input signal, x[k], to a few (1-6) bits, and the large amount of quantization noise generated is shaped to a high-frequency to make the in-band noise negligible. The out-of-band quantization noise is suppressed by a dedicated low-pass filter in case of a ΔΣ DAC or by loop dynamics in case of a ΔΣ FN-PLL.
In practice, non-linearity of the circuit building blocks poses a bottleneck to realize high-performance ΔE DACs and ΔΣ FN-PLLs. The non-linearity causes shaped out-of-band noise to fold intermodulation products into the baseband and limits the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise plus Distortion Ratio (SNDR) of ΔE DACs and phase noise and spurious performance of ΔΣ FN-PLLs.
Non-Linearity Impact on a Quantization Noise Cancellation
ΔE DACs using a 1-bit DAC unit offer inherently high-linearity but at the expense of a large quantization error. Consequently, achieving high in-band Signal-to-Noise Ratio (SNR) requires a very large oversampling ratio. Therefore, its usage is typically limited to low-bandwidth applications like audio and sensor interfaces. Using a multi-bit DAC effectively reduces the amount of quantization noise and considerably relaxes the oversampling ratio required to achieve high-bandwidth. But this comes at the expense of high sensitivity to the mismatch between DAC unit cells.
To improve matching between DAC unit cells, thermometer coding implementation is recommended. To get a better tradeoff between linearity and area, as the number of bits in the DAC increases, DAC implementation is usually segmented into two smaller DACs: an m1-bit coarse DAC and an m2-bit fine DAC. While the original modulator output x0[k] contains shaped noise, the split coarse x1[k], and fine x2[k], signals contain non-shaped noise as well as distortion. Adding DAC1 and DAC2 outputs with the proper gain ratio (gDAC1=2m2gDAC2) cancels these distortion components and restores the noise shaping properties. But in the presence of a gain error between the two DACs, noise and distortion from each individual path will leak into the output and cause severe performance degradation.
A segmented ΔE DAC architecture may use a Quantization Noise Cancellation (QNC) technique to overcome this limitation. By re-quantizing the original modulator output x0[k] using a second ΔΣ modulator to drive DAC1, coarse DAC1 control x1[k] now contains noise-shaped components besides the signal. Since signal x2[k] is the difference between the input and output of the ΔΣ modulator, it represents only the shaped quantization noise and does not contain any signal components. As a result, any spectral leakage due to improper gain ratio results only into noise-shaped signal that contributes little in-band energy.
Similarly, QNC techniques may be used to improve the performance and extend the bandwidth of ΔΣ fractional-N phase-locked loops (FN-PLLs). FIG. 1 shows a prior-art analog FN-PLL. Phase-Frequency Detector and Charge Pump (PFD/CP) 102 compares a reference clock REF to a divided clock DIV to control a charge pump that charges loop filter 104 go generate control voltage Vc that controls the frequency generated by Voltage-Controlled Oscillator (VCO) 106. VCO 106 output OUT is fed back to Multi-Modulus Divider (MMD) 108 to generate the divided clock DIV. MMD 108 can be a ΔΣ fractional divider in the feedback path. VCO 106 generates an output signal, OUT, of frequency FOUT=(NDIV+αDIV)FREF, where NDIV is a positive integer, αDIV is a fractional value between 0 and 1, and FREF is the frequency of the reference clock signal REF. Fractional-N operation is achieved by dithering the feedback multi-modulus divider MMD 108 using ΔΣ modulator 110, where the average of the dithered signal xDIV[k] corresponds to the desired fractional factor αDIV. The ΔΣ fractional divider, MMD 108, resembles a digital-to-frequency converter, where its shaped frequency quantization noise can be cancelled as for ΔΣ-DACs. Here, the quantization noise cancellation path, ΔΣ QNC 120, includes adder 112, digital accumulator 114 for frequency-to-phase conversion, and current DAC 116 to cancel quantization noise at the charge pump output using adder 118. In practice, the gain mismatch between DAC 116 and the signal path through PFD/CP 102 results in an imperfect QNC.
The fractional divider quantization noise impacts both analog and digital FN-PLLs alike. QNC techniques for digital FN-PLLs may use Time-to-Digital Converters (TDCs) and Digital-to-Time Converters (DTCs). Even though the cancellation gain path can be accurately calibrated using a Least-Mean Square (LMS) technique, each of the PFD/CP signal and DAC noise cancellation paths has different non-linear characteristics, namely pCP(x) and pDAC(x), respectively. The non-linearity of these blocks can significantly limit the overall phase noise and spurious performance of FN-PLLs. Similarly, coarse and fine DACs of a segmented ΔΣ-DAC architecture can have different non-linear characteristics, namely pDAC1(X) and pDAC2(x), and severely degrade SNDR and SFDR of the overall DAC.
The non-linearity of the signal path or noise cancellation path poses a bottleneck to realize high-performance ΔE DACs and ΔΣ FN-PLLs. The non-linearity causes shaped noise and tones in the high-frequency region of the multi-bit spectrum to fold intermodulation products into the baseband. The in-band distortion products cannot be readily removed by simple linear filters. Reducing system bandwidth may or may not significantly improve the SNDR and SFDR of ΔE DACs and phase noise and spurious performance of ΔΣ FN-PLLs. In this case, it is the non-linearity, rather than the quantization noise, that limits the performance of the system.
What is desired is adaptive non-linearity identification and compensation techniques that can be leveraged in the implementation of data converters, PLLs, and frequency synthesizers to achieve improved performance. An adaptive non-linearity identification and compensation circuit that is useful for various analog/mixed-signal/RF integrated circuits (ICs) building blocks is desired, including for clock generators, clock and data recovery (CDR), phase interpolators, voltage/current amplifiers, transimpedance amplifiers (TIAs), and power amplifiers (PAs).